Wide-scale deployment of full-duplex (FD) wireless networks requires analog SI canceller designs suitable for small-form-factor integration within an RF integrated circuit (RFIC).

The core technical challenge of analog SI cancellation is accurately reproducing the large delay spreads imposed by the multipath SI channel – a problem that has seen meaningful progress in IC design in recent years. However, RFIC capability alone is only one piece of the puzzle: it is the system-level challenges surrounding a practical FD radio that have thus far prevented widespread FD adoption..